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CS22230 mini pci / usb wireless controller 1 of 29 ds558pp1 rev. 1.0 www.cirrus.com 1 description the cirrus logic CS22230 wireless network controller enables high speed, 11 mbps digital wireless connectivity for a variety of platforms including embedded systems, mobile applications, and other cost sensitive applications capable of supporting a standard mini pci or usb interface . the CS22230 is a highly integrated single-chip mini pci / usb solution for wireless networks supporting video, audio, voice, and data traffic. the programmable controller executes cirrus logic?s whitecap?2 networking protocol that provides wi-fi? (802.11b) compliance as well as multimedia and quality of service (qos) support. the device includes several high performance components including an arm7tdmi risc processor core, a forward error correction (fec) codec and a wireless radio mac supporting up to 11 mbps throughput. the CS22230 is designed to support both a standard mini pci 2.2 compliant interface or usb 1.1 compliant device interface, making it an ideal choice for cost effective standalone and multifunction embedded high-speed wireless networking products. the CS22230 utilizes state-of-the-art 0.18um cmos process and is housed in a 208 mqfp package designed to provide integrated low cost ieee 802.11 standard compliant system solutions. the core is powered at 1.8 v to reduce overall power consumption. in addition, the CS22230 supports various power management modes for host, mac, baseband, and radio interfaces. figure 1. example system block diagram CS22230 data sheet wireless mini pci / usb controller 2.4 ghz direct sequence s p read s p ectru m 11 mbps wireless baseband i/f CS22230 wireless network controller 802.11b compatible 2.4 ghz digital radio phy transceiver system memory sdram (up to 4mb) sram (up to 256kb) usb / mini pci host boot rom/flash (upto1mb)
CS22230 mini pci / usb wireless controller 2 of 29 ds558pp1 rev. 1.0 www.cirrus.com 2 features embedded arm core and system support logic ? high performance arm7tdmi risc processor core at 77mhz ? 4kb integrated, one-way set associative, unified, write through cache ? individual interrupt for each functional block ? two 23-bit programmable (periodic or one-shot) general purpose timers ? 8 dword (32-bits) memory write and read buffers for high system performance ? abort cycle detection and reporting for debugging ? arm performance monitoring function for system fine-tuning ? programmable performance improvement logic based on system configuration ? flexible independent dma engines for mini pci and digital radio functional units enhanced memory controller unit ? programmable memory controller unit supporting sdram /async sram/boot rom interface ? 16-bit data bus with 12-bit address supporting up to 4mb at up to 103mhz sdram ? 8-bit data bus with addressing support up to 1mb of boot rom/flash ? programmable sdram timing and size parameters such as cas latencies and number of banks columns and rows fec codec ? high performance reed-solomon coding for error correction (255:239 block coding) ? reduces symbol error probability of a typical 10e-3 error rate environment to 10e-9 ? programmable rate fec engine to optimize channel efficiency ? low latency, fully pipelined hardware encoding and decoding. support byte wise single cycle throughput up to 77mhz, with a sustain rate of 77mbps. ? double buffering (64 dword read/write buffer) to enhance system performance ? on the fly configuration of encoder and decoder digital wireless radio mac ? glue-less interface to 802.11b radio baseband transceiver ? 11mbps data rate ? 32 dword transmit/receive fifo ? supports clear channel assessment (cca) power management ? host (mini pci) acpi compliant ? remote usb host wakeup ? supports variable rate radio transmit, receive and standby radio power modes through two dacs clock and pll interface ? single 44mhz crystal oscillator reference clock for mini pci version. 48mhz reference clock required in usb option. ? internal pll to generate internal and on board clocks usb controller interface ? 12 mbps usb 1.1 compliant device ? supports 1 to 16 endpoints, endpoints can be bulk, isochronous or interrupt ? variable endpoint buffer depths providing maximum flexibility for endpoint configurations ? flexible configuration programming via eeprom or firmware download ? remote host wakeup
CS22230 mini pci / usb wireless controller 3 of 29 ds558pp1 rev. 1.0 www.cirrus.com mini pci controller interface ? 33mhz 5v/3.3v mini pci 2.2 compliant master/target 32-bit data interface ? arm communication with mini pci controller through simple mailbox scheme ? generic mini pci controller programming interface ? flexible configuration programming via eeprom chip processing and packaging ? 208 mqfp package and 0.18 um state-of-the-art cmos process ? 1.8 v core for low power consumption. 3.3v i/o and 5v tolerant important notice "preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in this material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is subject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. use of this product in any manner that complies with the mpeg-2 video standard as defined in iso documents is 13818-1 (including annexes c, d, f, j, and k), is 13818-2 (including annexes a, b, c, and d, but excluding scalable extensions), and is 13818-4 (only as it is needed to clarify is 13818-2) is expressly prohibited without a license under applicable patents in the mpeg-2 patent portfolio, which license is available from mpeg la, l.l.c. 250 steele street, suite 300, denver, colorado 80296.
CS22230 mini pci / usb wireless controller 4 of 29 ds558pp1 rev. 1.0 www.cirrus.com 3 functional description figure 2. block diagram of major functional units system memory radio interface fec codec comm buffer mini pci interface dma ctr usb / mini pci host interface misc. config. clock/pll oscillator memory/boot rom controller arbiter dual radio mac w/ dma ctrl dma dma arm 7tdmi 4kb cache timer (2) interrupt controller read/write buffer 77mhz system control bus sleep timer jtag/test interface 44mhz usb interface 12mhz or 33 mhz 48mhz / 44 mhz
CS22230 mini pci / usb wireless controller 5 of 29 ds558pp1 rev. 1.0 www.cirrus.com 3.1 embedded arm core and system support logic the processing elements of the CS22230 include the arm7tdmi core and its associated system control logic. the arm processor and system controller consists of a memory management unit, 4-kb write through cache controller, 20 irq and 4 firq interrupt controller, and 2 general purpose timers. the arm processor and integrated system support logic provide the necessary execution engine to support a real time multi-tasking operating system, the network protocol stack, and firmware services. in addition, system performance monitor logic is included to aid in system performance fine-tuning (e.g. cache hit, cpi numbers). memory management unit arm instructions and data are fetched from system memory a cache-line (4/8 ? dwords /programmable) at a time when caching is turned on. during a cache line fill, critical word data, i.e., the access that caused the miss, is forwarded to the arm and also written into the data ram cache. the non-critical words in the line fetched following the critical word are then written to the cache on a dword basis, as they become available. memory writes are posted to dual 4-dwords (32-bit) memory write posting buffers. write posts use the sequential addressing feature on the memory bus. with dual buffering an out of sequence write will post to one write buffer while the other buffer is flushed to memory. there is one 8dword read buffers in the mem block. the buffer is used for both cacheable and non-cacheable memory space. interrupt controller the interrupt controller provides two interrupt channels to the arm processor. one interrupt channel is presented to the arm on its nfiq , and the other channel is presented on its nirq pin. these are referred to as the fiq channel and the irq channel. both channels operate in identical but independent fashion. the fiq channel has a higher priority on the arm processor than the irq channel. the interrupt controller includes a control register for each logical interrupt in the arm complex. the control register serves the following main purposes: ? provides the mapping between the ext_int inputs (physical interrupts) and the logical interrupt ? selects the particular type of signaling expected on the ext_int inputs: level, edge, active level high/low etc. ? enables or disables a logical interrupt
CS22230 mini pci / usb wireless controller 6 of 29 ds558pp1 rev. 1.0 www.cirrus.com 3.2 digital wireless radio interface the CS22230 digital radio mac i/f supports multiple radio baseband and rf interfaces. the baseband registers can be programmed during the configuration time using the control port interface. the mac also provides the capability of programming the signal, service and length on per packet basis without arm intervention. this significantly improves the performance of the system. there are three primary digital interface ports for the CS22230 that are used for configuration and during normal operation. these ports are: ? the control port, which is used to configure, set power consumption modes, write and/or read the status of the radio base band registers. ? the tx port, which is used to output the data that needs to be transmitted from the network processor. ? the rx port, which is used to input the received demodulated data to the network processor. 3.3 fec codec the fec codec performs reed-solomon code encoding to protect the data before it is transmitted to a noisy channel. it is a similar code as employed by digital broadcast industry, such as itu-t j.83 for dvb. the rs(255, 239) code implemented by the swg2710 can reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate environment. the encoder/decoder can be programmed to vary the coding block length ( n ) and correctable error ( t ) to optimize the tradeoff between channel utilization and data protection. the range of n iscurrentlysettobefrom50to255,andthe t is 8. the symbol size is fixed at 8 bits. coding parameters can be set real time, allowing maximum flexibility for the system to adjust the fec setting, such as block size, in order to optimize channel efficiency. the encoder also has a very low latency of two cycles. both the encoder and decoder are fully pipelined in structure to achieve single cycle throughput. the fec can be disabled in firmware.
CS22230 mini pci / usb wireless controller 7 of 29 ds558pp1 rev. 1.0 www.cirrus.com 3.4 programmable memory controller the CS22230 incorporates a general-purpose memory controller that supports a sdram/async sram memory and flash memory interface. in the ram configuration, the system memory interface supports up to 16-mbyte of 16-bit sdram running at a frequency up to 103 mhz single-state access cycles or 256kb of 16 bit async sram. the memory controller provides programming of sdram parameters such as cas latency, refresh rate, etc; these registers are located in miscellaneous configuration registers. when there are no pending memory requests from any internal requester, the swg2110 will keep clock enable (cke) signal low to cause the sdram to stay in power down mode. once a memory request is active, the swg2110 will assert cke high to cause the sdram to come out of power down mode. typically, this can reduce memory power consumption by up to 50%. in rom configuration, firmware for CS22230 is stored in non-volatile memory and is accessed through the boot rom interface. the maximum addressable rom space supported is 1mb. rom read/write and output enable are shared with ram control pins. the rom can be re-flashed allowing for software upgrades. 3.5 mini pci controller interface embedded in the CS22230 is a mini pci 2.2 fully compliant master/target 32 bit data interface including power management support (pme signal). the communication buffer logic was designed to be flexible and generic to both the pc software and arm firmware. mini pci data transfer is supported by a dma control block (dcb). the dcb is configured by the arm, allowing the arm to control how often it is interrupted. mini pci data transfers are done by the mini pci master, and the dcb, offloading cpu overhead. 3.6 usb interface embedded within the CS22230 is a full speed usb 1.1 compliant device interface. the device supports from 1 to 16 endpoints and is completely programmable via firmware download or external eeprom. all ?setup? commands are passed to the system processor for interpretation. the device also contains a dma engine to transfer arbitrary amounts of data to and from main memory before interrupting the system processor.
CS22230 mini pci / usb wireless controller 8 of 29 ds558pp1 rev. 1.0 www.cirrus.com 4 pinout and signal descriptions figure 3. CS22230 logical pin groupings (note: not all signals are shown) nrst nperr, nserr txclk txpe txd txrdy cca bbrnw nresetbb txpebb nbbcs bbas txpape bbsclk bbsdx synthle rxpebb nrpd rxd mdrdy rxcl k digital wireless radio CS22230 wireless network controller smclk sma[11:0] nsmcs[1:0] nsmras nsmcas smd[15:0] nsmwe smdqm[1:0] system memory interface smcke jtag interface xtalclkin xtalout tdo tdi tck ad[31:0] ncbe[3:0] idsel nframe nirdy ntrdy nrst nstop ndevsel ninta pclk mini pci controller interface tms ntrst nbrce clock interface xtraclk pllagnd pllavcc plldgnd plldvcc pllplus pll power interface nperr ngnt nreq par pme nserr system and pci reset ntest dacavcc & dacagnd clkrun wc_wifi usbvpx usbvmx usb interface usb_enum
CS22230 mini pci / usb wireless controller 9 of 29 ds558pp1 rev. 1.0 www.cirrus.com this section provides detailed information on the CS22230 signals. the signal descriptions are useful for hardware designers who are interfacing the CS22230 with other devices. system memory interface the system memory interface supports standard sdram interface, async sram and flash. there are total of 37 signals in this interface. smclk output system mem clock for sdram. currently the interface supports 103 mhz for a maximum bandwidth of 200mbytes/sec. nsmcs0 output chip select bit 0. this signal is used to select or deselect the sdram for command entry. when smncs is low it qualifies the sampling of nsmras, nsmcas and nsmwe. also used as testmode(2) when ntest pin is '0'. nsmcs output chip select bit 1. nbrce output chip select for rom access. this signal is used to select or deselect the boot rom memory. nsmras output row address select. used in combination with nsmcas, nsmwe and nsmcs to specify which sdram page to open for access. also used during reset to latch in the strap value for clk_bypass; if set to a '1' implies bypassing clock module; whatever clk is applied on the input clock is used for memclk and ctlclk. also shared as the romoe signal. nsmcas output column address select. used in combination with nsmras, nsmwe and nsmcs to specify which piece of data to access in selected page. also used during reset to latch in the strap value for same_freq; if set to a '1' implies internal mem_clk and arm_clk are running at the same frequency and 180 degrees out of phase. nsmwe output write enable. used in combination with nsmras, nsmcas, and nsmwe to specify whether the current cycle is a read or a write cycle. also used during reset to latch in the strap value for tst_bypass; if set to a '1' implies pll bypass. also shared as the romwe to do flash programming. smdqm[1:0] output data mask bit 1:0. these signals function as byte enable lines masking unwanted bytes on memory writes. also used as testmode(1:0) when ntest pin is '0'. smcke output clock enable. smcke is used to enable and disable clocking of internal ram logic.
CS22230 mini pci / usb wireless controller 10 of 29 ds558pp1 rev. 1.0 www.cirrus.com sma0 output address bit0. the address bus specifies either the row address or column address. also shared as boot-rom address bit0. this pin should be pull- down. sma1 output address bit1. also shared as boot-rom address bit1. also used during reset to latch in the strap value for mini pci sel; if set to a '1' implies mini pci mode. sma2 output address bit2. also shared as boot-rom address bit2. also used during reset to latch in the strap value for usbsel; if set to a '1' implies usb mode. sma3 output address bit3. also shared as boot-rom address bit3. this pin should be pull-down. sma4 output address bit4. also shared as boot-rom address bit4. also used during reset to latch in the strap value for romcfg; if set to a '1' implies mini pci configuration data should be downloaded from rom. sma5 output address bit5. also shared as boot-rom address bit5. also used during reset to latch in the strap value for test_rst_enb; if set to a '0' implies normal operation mode. sma6 output address bit6. also shared as boot-rom address bit6. also used during reset to latch in the strap value for freq_sel(0). freq_sel(2:0) is used to select the multiplication factor for the internal pll (000=1x, and 111=8x). sma7 output address bit7. also shared as boot-rom address bit7. also used during reset to latch in the strap value for freq_sel(1). freq_sel(2:0) is used to select the multiplication factor for the internal pll (000=1x, and 111=8x). sma8 output address bit8. also shared as boot-rom address bit8. also used during reset to latch in the strap value for freq_sel(2). freq_sel(2:0) is used to select the multiplication factor for the internal pll (000=1x, and 111=8x). sma9 output address bit9. also shared as boot-rom address bit9. also used during reset to latch in the strap value for sdram_delay(0). sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments).
CS22230 mini pci / usb wireless controller 11 of 29 ds558pp1 rev. 1.0 www.cirrus.com sma10 output address bit10. also shared as boot-rom address bit10. also used during reset to latch in the strap value for sdram_delay(1). sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments). sma11 output address bit11. also shared as boot-rom address bit11. also used during reset to latch in the strap value for sdram_delay(2). sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments). smd[7:0] bi-directional data bus. the data bus contains the data to be written to memory on a writecycleandthereadreturndataonareadcycle. smd[15:8] bi-directional shared data bus. the data bus contains the data to be written to ram memoryonawritecycleandthereadreturndataonareadcycle.databit [15:8] is also shared as boot rom address bit [19:12]. digital wireless radio interface all radio input buffers are schmitt triggered input buffers. there are total of 21 signals in this interface. txclk input transmit clock is a clock input from the radio baseband processor. this signal is used to clock out the transmit data on the rising edge of txclk. txpebb output baseband transmit power enable, an output from the mac to the radio baseband processor. when active, the baseband processor transmitter is configured to be operational, otherwise the transmitter is in standby mode. txd output it is the serial data output from the mac to the radio baseband processor. the data is transmitted serially with the lsb first. the data is driven by the mac on the rising edge of txclk and is sampled by the radio baseband processor on the falling edge of txclk (in 3824 mode) and rising edge of txclk (in 3860b mode). txrdy input transmit data ready is an input to the mac from the radio baseband processor to indicate that the radio baseband processor is ready to receive the data packet over the txd signal. the signal is sampled by the mac on the rising edge of txclk. cca input clear channel assessment is an input from the radio baseband processor to signal that the channel is clear to transmit. when this signal is a 0, the channel is clear to transmit. when this signal is a 1, the channel is not clear to transmit. this helps the mac to determine when to switch from receive to transmit mode.
CS22230 mini pci / usb wireless controller 12 of 29 ds558pp1 rev. 1.0 www.cirrus.com bbrnw output baseband read/write is an output from the mac to indicate the direction of the sd bus when used for reading or writing data. this signal has to be setup to the rising edge of bbsclk for the baseband processor and is driven on the falling edge of bbsclk. nresetbb output baseband reset is an output of the mac to reset the baseband processor. bbas output baseband address strobe is used to envelop the address or the data on the bbsdx bus. logic 1 envelops the address and a logic 0 envelops the data. this signal has to be setup to the rising edge of bbsclk for the baseband processor and is driven on the falling edge of bbsclk. nbbcs output baseband chip select is an active low output to activate the serial control port. when inactive the sd, bbsclk, bbas and bbrnw signals are ?don?t cares?. txpape output radio power amplifier power enable is a software-controlled output. this signal is used to gate power to the power amplifier. txpe output radio transmit power enable indicates if transmit mode is enabled. when low, this signal indicates receive mode. rxpebb output baseband receive power enable is an output that indicates if the mac is in receive mode. output to baseband processor enables receive mode in baseband processor. bbsclk output baseband serial clock is a programmable output generated by dividing arm_clk by 14 (default). this clock is used for the serial control port to sample the control and data signals. bbsdx bi-directional baseband serial data is a bi-directional serial data bus, which is used to transfer address and data to/from the internal registers of the baseband processor. synthle output synthesizer latch enable is an active high signal used to send data to the synthesizer. nrpd output radio powerdown enable. this active low signal is used for power management purposes for the radio circuitry.
CS22230 mini pci / usb wireless controller 13 of 29 ds558pp1 rev. 1.0 www.cirrus.com rxclk input this is an input from base band processor. it is used to clock in received data from base band processor. mdrdy input receive data ready is an input signal from the baseband processor, indicating a data packet is ready to be transferred to the mac. the signal returns to inactive state when there is no more receiver data or when the link has been interrupted. this signal is sampled on the falling edge of rxclk (in 3824 mode), and sampled at rising edge of rxclk (in 3860b mode). rxd input receive data is an input from the baseband processor transferring demodulated header information and data in a serial format. the data is frame aligned with md_rdy. this signal is sampled on the falling edge of rxclk (in 3824 mode), and sampled at rising edge of rxclk (in 3860b mode). dacavcc input analog power for dac. 3.3v input. dacagnd input analog ground for dac. pll and clock interface there are three clock pins and five pll power pins. there are a t of 8 signals in this interface. xtal_clkin input 44 mhz reference clock input/crystal clock input for mini pci and 48 mhz for usb. xtalout output reference crystal clock output. xtraclk input second clock input to clock module. this input allows independent control for mem_clk and ctl_clk. the usage of this clock input is determined by the clk module configuration, which is determined by the three strapping input pin values.
CS22230 mini pci / usb wireless controller 14 of 29 ds558pp1 rev. 1.0 www.cirrus.com pllagnd input analog pll ground. pllavcc input analog pll power. 3.3v input. plldgnd input digital pll ground. plldvcc input digital pll power. 1.8v input. pllplus input analog pll ground. mini pci interface the mini pci interface is a standard 2.2 compliant interface. there are a total of 52 signals. ad[31:0] bi-directional mini pci address/data. this bus contains a physical address during the first clock of a mini pci transfer and data during subsequent clocks. the signals are inputs during the address and write data phases of a transaction, or outputs during the read data phase of a transaction. ncbe[3:0] bi-directional control/byte enable. this bus defines the bus command during the first clock of a mini pci transaction and the data byte enables during subsequent clocks. idsel i/o od mini pci initialization device select. used as a chip select during configuration read and write cycles. nframe bi-directional mini pci cycle frame. this signal marks the beginning and duration of a current bus cycle. nirdy bi-directional mini pci initiator ready. irdy holds off the beginning of a write cycle and the completion of a read cycle until sampled active. ntrdy bi-directional mini pci target ready. this signal is driven active to indicate that write data has been sampled or that read data has been delivered. ndevsel bi-directional mini pci device select. as a medium speed device, this signal is driven active two mini pci clocks after nframe is sampled active indicating a positive decode. it remains active until the end of the transaction.
CS22230 mini pci / usb wireless controller 15 of 29 ds558pp1 rev. 1.0 www.cirrus.com nstop bi-directional mini pci stop. this signal indicates a target initiated termination of the current cycle. ninta output/open drain mini pci interrupt request a. generates an interrupt on the mini pci bus. nclkrun i/o od mini pci clock run. this signal is an optional signal used by devices to indicate the clock status. pclk i/o od mini pci clock. typically a 33 mhz. all CS22230 mini pci activity is synchronous to pclk. nperr bi-directional mini pci parity error. this signal is asserted two clocks after a data parity error is detected on the mini pci bus. nserr output/open drain mini pci system error. this open drain signal is used to indicate a fatal parity error on mini pci address. nreq input mini pci master request. used by the mini pci master to indicate it needs drive the mini pci bus. ngnt bi-directional mini pci master grant. used by the mini pci master to indicate ok to drive the mini pci bus. par bi-directional mini pci parity. this signal is asserted one clock after data transfer has occurred on the mini pci bus. pme output/open drain power management event. use to let the system knows a change in power management event has occurred. system reset nrst input system reset and mini pci reset. reset is an asynchronous signal that forcesthechiptogotoaknownstate.thisisanactivelowsignal. usb interface usbvp bi-directional differential usb data plus. for high-speed mode, this signal is pull up to 5 volt during idle state (see usb_enum).
CS22230 mini pci / usb wireless controller 16 of 29 ds558pp1 rev. 1.0 www.cirrus.com usbvm bi-directional differential usb data minus. usb_enum output usb enumeration ? indicates disconnect/connect event. usb_enum is used to pull the d+ line high, indicating to the host or hub a usb bus ?full rate? connection is active. debug interface tdo output test data output. tdi input test data input. the input has an integral pull up. tck input test clock signal. tms input test mode select. the input has an integral pull up. ntrst input test interface reset. the input has an integral pull up. miscellaneous interface spio_8,12,13,16 bi-directional special purpose i/o reserved for supporting custom interfaces. note: spio 13 is used for usb_enum during usb modes. ntest input chip test mode pin. used in conjunction with smncs0, smdqm[0:1]. pull up for normal operation. power and ground vcc (5v and 3.3v) 1 input 5v inputs. there are a total of 3 pins. vdd (3.3v) input 3.3v inputs. there are a total of 26 pins. vee (1.8v) input 1.8 inputs to the core. there are a total of 9 pins. vss input ground. there are a total of 33 pins. 1 5v or 3.3v depending on desired pci configuration
CS22230 mini pci / usb wireless controller 17 of 29 ds558pp1 rev. 1.0 www.cirrus.com figure 4. CS22230 208 pin fpbga pinout diagram
CS22230 mini pci / usb wireless controller 18 of 29 ds558pp1 rev. 1.0 www.cirrus.com table 1. pin listing by ball ball name ball name ball name ball name a01 vcc c12 n/c g16 vdd n04 par a02 ext_nreset c13 dacavss g17 rxclk n14 sma06 a03 ad31 c14 xtalclkin h01 ncbe02 n15 sma08 a04 ngnt c15 vdd h02 vss n16 vss a05 vss c16 cca h03 ad16 n17 vdd a06 vdd c17 vss h04 ad18 p01 vdd a07 clkrun d01 ad24 h14 bbsd p02 ad13 a08 usbvp d02 vdd h15 bbrnw p03 ad12 a09 vee d03 ad25 h16 vss p04 ncbe00 a10 tck d04 ad28 h17 bbas p05 vdd a11 vss d05 pme j01 vcc p06 ad02 a12 vdd d06 n/c j02 vss p07 smncs01 a13 n/c d07 vss j03 vee p08 vss a14 vss d08 vss j04 vee p09 vdd a15 pllplus d09 vdd j14 vee p10 vss a16 pllagnd d10 tms j15 vdd p11 vss a17 plldvcc d11 dacavdd j16 bbsclk p12 smclk b01 ad27 d12 rsvd j17 synthle p13 smd07 b02 pcd10 d13 xtalout k01 ntrdy p14 sma02 b03 ad30 d14 pllavcc k02 nframe p15 sma05 b04 nreq d15 txd k03 vdd p16 vdd b05ninta d16txrdy k04vss p17sma07 b06 vdd d17 txclk k14 ntest r01 vss b07 n/c e01 ad23 k15 vss r02 ad10 b08 vee e02 ncbe03 k16 vee r03 ad09 b09 vss e03 idsel k17 bbncs r04 ad05 b10 tdi e04 vss l01 nperr r05 vss b11 vdd e14 spio13 l02 vss r06 smncs00 b12 rsvd e15 txpebb l03 ndevsel r07 smdqm01 b13 xtraclk e16 txpape l04 nirdy r08 smd00 b14 vdd e17 vdd l14 smnwe r09 vee b15 plldgnd f01 ad20 l15 nbrce r10 smd02 b16 rnpd f02 ad22 l16 smnras r11 smd05 b17 txpe f03 vss l17 vss r12 smd06 c01 ad26 f04 vdd m01 vss r13 smd09 c02 ad29 f14 rxd m02 vdd r14 smd12 c03 vss f15 spio12 m03 nserr r15 smd15 c04 vdd f16 vss m04 nstop r16 vss c05 pclk f17 rxpebb m14 sma09 r17 sma04 c06 spio8 g01 ad17 m15 sma11 t01 ad11 c07 usbvm g02 ad19 m16 sma10 t02 vcc c08 vss g03 vdd m17 vss t03 ad08 c09 vee g04 ad21 n01 ad14 t04 ad06 c10 tdo g14 nresetbb n02 ncbe01 t05 ad03 c11 ntrst g15 mdrdy n03 ad15 t06 ad00
CS22230 mini pci / usb wireless controller 19 of 29 ds558pp1 rev. 1.0 www.cirrus.com ball name ball name ball name ball name t07 smdqm00 t14 vdd u04 ad04 u11 vss t08 smcke t15 vss u05 ad01 u12 smd08 t09 vee t16 sma00 u06 vdd u13 smd10 t10 smd01 t17 sma03 u07 smncas u14 smd11 t11 smd04 u01 vdd u08 vss u15 smd13 t12 vdd u02 vss u09 vdd u16 smd14 t13 vss u03 ad07 u10 smd03 u17 sma01
CS22230 mini pci / usb wireless controller 20 of 29 ds558pp1 rev. 1.0 www.cirrus.com table 2. pin listing by name ball name ball name ball name ball name t06 ad00 a13 n/c m15 sma11 b06 vdd u05 ad01 b07 n/c t08 smcke b11 vdd p06 ad02 c12 n/c p12 smclk b14 vdd t05 ad03 d06 n/c r08 smd00 c04 vdd u04 ad04 l15 nbrce t10 smd01 c15 vdd r04 ad05 p04 ncbe00 r10 smd02 d02 vdd t04 ad06 n02 ncbe01 u10 smd03 d09 vdd u03 ad07 h01 ncbe02 t11 smd04 e17 vdd t03 ad08 e02 ncbe03 r11 smd05 f04 vdd r03 ad09 l03 ndevsel r12 smd06 g03 vdd r02 ad10 k02 nframe p13 smd07 g16 vdd t01 ad11 a04 ngnt u12 smd08 j03 vdd p03 ad12 b05 ninta r13 smd09 j04 vdd p02 ad13 l04 nirdy u13 smd10 j14 vdd n01 ad14 l01 nperr u14 smd11 j15 vdd n03 ad15 b04 nreq r14 smd12 k03 vdd h03 ad16 g14 nresetbb u15 smd13 m02 vdd g01 ad17 m03 nserr u16 smd14 n17 vdd h04 ad18 m04 nstop r15 smd15 p01 vdd g02 ad19 k14 ntest t07 smdqm00 p05 vdd f01 ad20 k01 ntrdy r07 smdqm01 p09 vdd g04 ad21 c11 ntrst u07 smncas p16 vdd f02 ad22 n04 par r06 smncs00 t12 vdd e01 ad23 b02 pcd10 p07 smncs01 t14 vdd d01 ad24 c05 pclk l16 smnras u01 vdd d03 ad25 a16 pllagnd l14 smnwe u06 vdd c01 ad26 d14 pllavcc e14 spio13 u09 vdd b01 ad27 b15 plldgnd c06 spio8 a09 vee d04 ad28 a17 plldvcc j17 synthle b08 vee c02 ad29 a15 pllplus a10 tck c09 vee b03 ad30 d05 pme b10 tdi k16 vee a03 ad31 b16 rnpd c10 tdo r09 vee h17 bbas g17 rxclk d10 tms t09 vee k17 bbncs f14 rxd d17 txclk a05 vss h15 bbrnw f17 rxpebb d15 txd a11 vss j16 bbsclk t16 sma00 e16 txpape a14 vss h14 bbsd u17 sma01 b17 txpe b09 vss c16 cca p14 sma02 e15 txpebb c03 vss a07 clkrun t17 sma03 d16 txrdy c08 vss d11 dacavdd r17 sma04 c07 usbvm c17 vss c13 dacavss p15 sma05 a08 usbvp d07 vss d12 rsvd n14 sma06 a01 vcc d08 vss b12 rsvd p17 sma07 j01 vcc e04 vss a02 ext_nreset n15 sma08 t02 vcc f03 vss e03 idsel m14 sma09 a06 vdd f16 vss g15 mdrdy m16 sma10 a12 vdd h02 vss
CS22230 mini pci / usb wireless controller 21 of 29 ds558pp1 rev. 1.0 www.cirrus.com ball name ball name ball name ball name h16 vss m17 vss r16 vss c14 xtalclkin j02 vss n16 vss t13 vss d13 xtalout k04 vss p08 vss t15 vss b13 xtraclk k15 vss p10 vss u02 vss l02 vss p11 vss u08 vss l17 vss r01 vss u11 vss m01 vss r05 vss f15 wc_wifi
CS22230 mini pci / usb wireless controller 22 of 29 ds558pp1 rev. 1.0 www.cirrus.com 5 specifications table 3. absolute maximum ratings symbol parameter limits units v ee voltage at core 1.62 to 2.0 v v dd dc supply ( i/o) -0.3 to 3.9 v v in (mini pci ) mini pci voltage -0.5 to 5.25 v v in input voltage -0.1 to vdd + 0.33 v i in dc input current +/- 10 a xtalin input frequency 1 0to60 mhz t stgp storage temperature range -40 to 125 c notes: 1. the xtalin & xtalout pins have minimal esd protection. 2. this device may have esd sensitivity above 500v hbm per jesd22-a114. normal esd precautions need to be followed. table 4. recommended operating conditions symbol parameter limits units v dd vcc vee dcsupply 3.0to3.60(3vi/o) 4.5to5.5(5vi/o) 1.6 to 2.0 (core) v xtalclkin input frequency 44 or 48 mhz armclk internal arm clock frequency 44(4x11) to 77 mhz memclk internal memory clock frequency 72 to 103 mhz f tck jtag clock frequency 0 to 10 mhz t a ambient temperature 0 to +70 c t j junction temperature 0 to +105 c table 5. capacitance symbol parameter value units c in input capacitance 3.4 pf c out output capacitance 4.0 pf
CS22230 mini pci / usb wireless controller 23 of 29 ds558pp1 rev. 1.0 www.cirrus.com table 6. dc characteristics symbol parameter condition min typ max units v il voltage input low -0.5 0.8 v v ih voltage input high 2.0 vcc + 0.5 v v ol voltage output low i ol = 1500 a 0.55 v v oh voltage output high i oh =-500 a 0.24 v i il input leakage current v in =v ss or v dd -10 10 a i oz 3-state output leakage current v oh =v ss or v dd -10 10 a i cc &i dd i ee dynamic supply current note 1 v cc & dd = 5v & 3.3v v dd =1.8v 35 135 ma 5.1 ac characteristics and timing table 7. system memory interface timing parameter parameter description min max units t d smd smclk to smd[31:0] output delay 7 ns t d sma smclk to sma[11:0] output delay 4.7 ns t d smdqm smclk to smdqm[3:0] output delay 5.1 ns t d smncs smclk to smncs[1:0] output delay 4.1 ns t d smnwe smclk to smnwe output delay 4.5 ns t d smcke smclk to smcke output delay 4.3 ns t d smncas smclk to smncas output delay 4.0 ns t d smnras smclk to smnras output delay 5.0 ns t per smclk smclk period 72 103 ns t su smd smd[31:0] setup to smclk 1.0 ns t h smd smd[31:0] hold from smclk 2.4 ns notes: 1. outputs are loaded with 35pf on smd, 25pf on sma, smdqm, smnras, and smncas and 20pf on smclk, smncs, and smcke. 2. an attempt has been made to balance the setup time needed by the sdram and the setup needed by CS22230 to read data. if there is a problem meeting setup on the sdram, there is a programmable delay line on smclk which can help meet the setup time. care must be taken, however, not to violate the setup on the return read data. the delay can be increased by a multiple of 0.25ns by using the sma[11:09] pins to selectively set the clock delay .
CS22230 mini pci / usb wireless controller 24 of 29 ds558pp1 rev. 1.0 www.cirrus.com smclk smd[15:0] sma[13:0] smdqm[1:0] smncs[1:0] smnwe smcke smnras smncas write data write data row addr column addr row addr t d smcke t d smnras t d smncas t d smnwe t d sma t d smd t d smdqm t d smncs figure 5. system memory interface ?write? timing diagram smclk smd[15:0] sma[13:0] smdqm[1:0] smncs[1:0] smnwe smcke smnras smncas data data row addr column addr row addr active active t per smclk t d smcke t d smnras t d smncas t d sma t d smncs t su smd t h smd figure 6. system memory interface 'read' timing diagram
CS22230 mini pci / usb wireless controller 25 of 29 ds558pp1 rev. 1.0 www.cirrus.com table 8. rom/flash memory read timing item symbol min max clock period (1) t per smclk 72 mhz 103 mhz ce to smd latched data (2) t id smd 221 ns oe de-asserted to oe asserted (3) t f smras 6(t per smclk ) rom address to output delay (4) t acc 220 ns smclk to sma output delay t d sma 4.0 ns smclk to brce output delay (ce) t d brce 4.5 ns smclk to smras output delay (oe) t d smras 5.0 ns smd setup to smclk t su smd 1.0 ns smd hold from smclk t h smd 2.4 ns 1. the memclock timing is derived by bootstrap pll settings. synchronous modes at 77 mhz & 72 mhz are currently supported. 2. t id smd is based on the fm_romrdlat register settings ? default is 09h max. (77mhz ~ 17 times smclk = 221ns). 3. t f smras is the minimum time required before the next oe is active on the bus (6 times smclk). the rom device must release the bus within this time frame (77mhz ~ 78 ns). 4. based on default fm_romrdlat register settings (note: 09h translates to 11h) see fm_romrdlat register settings for more information) smclk smd[7:0] sma[11:0], smd[13:8] smnwe brce (ce) smras (oe) data address t per smclk t d t d smras t d t ld smd t d brce t d smras brce t acc sma t su smd t h smd t f smras figure 7. rom memory interface 'read' timing diagram
CS22230 mini pci / usb wireless controller 26 of 29 ds558pp1 rev. 1.0 www.cirrus.com table 9. mini pci interface timings parameter parameter description min max units t d ad pclk to adx[31:0] output delay 10.93 ns t d ncbe pclk to ncbex[3:0] output delay 10.93 ns t d nframex pclk to nframex output delay 10.93 ns t d ndevselx pclk to ndevselx output delay 10.92 ns t d nirdyx pclk to nirdyx output delay 10.92 ns t d ntrdyx pclk to ntrdyx output delay 10.92 ns t d nstopx pclk to nstopx output delay 10.92 ns t d parx pclk to nparx output delay 10.92 ns t d nperrx pclk to nperrx output delay 10.93 ns t d nserr pclk to nserr output delay 10.93 ns t su all all inputs setup to pclk 5 ns t h all all inputs hold from pclk 1.1 ns notes: 1. all outputs are loaded with 50pf. table 10. usb interface timings parameter description min max units usbvpx differential data positive 4 20 ns usbvpm differential data negative 4 20 ns
CS22230 mini pci / usb wireless controller 27 of 29 ds558pp1 rev. 1.0 www.cirrus.com table 11. radio mac ac timings ? intersil modes parameter parameter description min max units t d bbas bbas output delay from falling bbsclk 8.2 ns t d bbrnw bbrnw output delay from falling bbsclk 8.0 ns t d nbbcs nbbcs output delay from falling bbsclk 59.0 ns t d bbsdx bbsdx output delay from falling bbsclk 7.0 ns t su bbsdx bbsdx setup to rising edge of bbsclk 14.8 ns t h bbsdx bbsdx hold from rising edge of bbsclk 0.0 ns t d txd txd output delay from rising txclk (smac mode) 33.5 ns t d txd txd output delay from rising txclk (rmac mode) 15.4 ns t su rxd rxdsetuptorisingedgeofrxclk 1.0 ns t h rxd rxd hold from rising edge of rxclk 1.8 ns t su mdrdy mdrdy setup to falling edge of rxclk 2 ns t h mdrdy mdrdy hold from falling edge of rxclk 1 ns t d txpebb txpebb output delay from rising txclk 15.0 ns t d rxpebb rxpebb output delay from rising rxclk 16.0 ns t su txrdy txrdy setup to falling edge of txclk 6.5 ns t h txrdy txrdy hold from falling edge of txclk 0 ns t duty rxclk 2 rxclk period see note ns t duty txclk 2 txclk period see note ns notes: 1. cca signal is double synchronized to armclkin. 2. armclk must be at least 4 times the txclk and rxclk frequency. 3. harris baseband (3824/3824a) generates rxclk and txclk of 4 mhz. the duty cycle varies between 33-40% with a high time of 90.9ns and low time that alternates between 136 and 182ns. the clock period varies between 227 and 272 ns, giving an effective period of 250ns. 4. txd delay in 802.11b mode is the result of sampling the txclk with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. in this table, ctlclk is assumed to have a 13 ns period. 5. bbncs output delay = [(1/armclk freq)*ceiling(ser_clk_div/2)] + 7ns, the specified value is based on armclk of 77 mhz and ser_clk_div=8.
CS22230 mini pci / usb wireless controller 28 of 29 ds558pp1 rev. 1.0 www.cirrus.com table 12. radio mac ac timings ? rfmd modes parameter parameter description min max units t d bbrnw bbrnw output delay from falling bbsclk 6.7 ns t d nbbcs nbbcs output delay from falling bbsclk 110.79 ns t d bbsdx bbsdx output delay from falling bbsclk 7.0 ns t su bbsdx bbsdx setup to rising edge of bbsclk 14.5 ns t h bbsdx bbsdx hold from rising edge of bbsclk 0.0 ns t d txd txd output delay from rising txclk (smac mode) 33.5 ns t d txd txd output delay from rising txclk (rmac mode) 15.4 ns t su rxd rxdsetuptorisingedgeofrxclk 1.0 ns t h rxd rxd hold from rising edge of rxclk 1.8 ns t su mdrdy mdrdy setup to falling edge of rxclk 2 ns t h mdrdy mdrdy hold from falling edge of rxclk 1 ns t d txpebb txpebb output delay from rising txclk 15.0 ns t d rxpebb rxpebb output delay from rising rxclk 16.0 ns t su txrdy txrdy setup to falling edge of txclk 6.5 ns t h txrdy txrdy hold from falling edge of txclk 0 ns notes: 1. cca signal is double synchronized to armclkin. 2. armclk must be at least 4 times the txclk and rxclk frequency. 3. txd delay in 802.11b mode is the result of sampling the txclk with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. in this table, ctlclk is assumed to have a 13 ns period. 4. bbncs output delay = [(1/armclk freq)*ceiling(ser_clk_div/2)] + 7ns, the specified value is based on armclk of 77 mhz and ser_clk_div=8. 5.2 table 13. package specifications symbol parameter value units jc junction-to-case thermal resistance 2.5 c/w ja junction-to-open air thermal resistance 26.9 c/w t j_max max junction temperature 105 c notes: 1. armclk / memclk = 77mhz
CS22230 mini pci / usb wireless controller 29 of 29 ds558pp1 rev. 1.0 www.cirrus.com 6 packaging the CS22230 controller is available in a 208 fine pitch ball grid array (fpbga) package. figure 8 contains the package mechanical drawing. figure 8. CS22230 fpbga-pin mechanical drawing

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